1. Field of the Invention
The present invention relates to the adjustment of duty cycles, and, in particular, to a programmable duty-cycle generator.
2. Description of the Related Art
In the context of circuits, a duty cycle is the ratio of time that a signal is high in relation to the time that the signal is low. In digital circuitry, including most computers, a clock signal is used to coordinate various actions within one or more circuits. The clock signal oscillates between a high and a low state and is usually a square wave having a 50% duty cycle. The circuits using the clock signal for synchronization may become active at either the rising edge, the falling edge, or both edges of the clock signal. As the clock signal traverses a path, its duty cycle may distort and require adjustment.
Duty-cycle adjustment at high speeds is frequently required in a variety of modern applications. For example, a memory component might require a particular duty cycle to allow for pre-charge time before being able to store information. Such high-speed duty-cycle adjustment is typically performed by an analog duty-cycle correction circuit that uses one or more operational amplifiers to try to force the common-mode duty cycle to 50% by comparison to a reference signal. If the common-mode duty cycle does not match the reference signal, then the current load is rapidly increased or decreased, usually consuming much power in the process. Analog circuits that adjust duty cycles to fixed values other than 50% consume even more power and suffer other disadvantages characteristic of analog circuitry, as well as lacking programmability of the desired duty cycle value.